1. Technical Field
The present invention relates to a semiconductor memory apparatus, and in particular, to a technology for repairing failures in a semiconductor memory apparatus.
2. Related Art
Semiconductor apparatuses, particularly semiconductor memory apparatuses, have fuse circuits for changing the internal configuration or programming the repair address. A set of fuses included in a fuse circuit store an address and specific configurations through fuse programming. The electrical connection resistive property of the fuse varies with changes in its electrical connection caused by the application of a laser beam or electrical stress. Specific information is programmed using such changes in the electrical connection state (short or open) of the fuse.
As a point of reference, a laser blowing-type fuse, in which the fuse link is cut by laser beams, is generally referred to as a physical fuse type. The laser beam irradiation is typically performed in a wafer state prior to the packaging of the semiconductor memory apparatus. In a packaged state, an electrical method is used rather than a physical method that uses laser beams. Fuses programmable in a packaged state are generally referred to as electrical fuses, meaning that such fuses may be programmed by changing their electrical connection state through the application of electrical stress. Such electrical fuses may be further categorized into anti-type fuses (hereinafter referred to as “anti-fuses”), which change from an open state to a short state, and blowing-type fuses, which change from a short state to an open state. These various types of fuses are selectively used based on consideration of various characteristics and the size of the semiconductor apparatus and semiconductor memory apparatus. In general, a fuse circuit includes a plurality of fuse sets, each of which may be programmed with a bit of specific address.
FIG. 1 is a configuration diagram illustrating a repair circuit of a typical semiconductor memory apparatus.
Referring to FIG. 1, the repair circuit of a semiconductor memory apparatus includes a plurality of fuse sets 10_0 to 10_N and a repair processing unit 20.
It is assumed that a specific repair address is programmed to each of the plurality of fuse sets 10_0 to 10_N. When an input address BXAR<2:11> is applied to the plurality of fuse sets 10_0 to 10_N, each fuse set outputs a plurality of hit signals HIT<0:9> by comparing the input address BXAR<2:11> with its repair address programmed in the fuse set, in response to the corresponding fuse set enable signal FSE0-FSEN.
The repair processing unit 20 replaces the memory block corresponding to the repair address with a redundancy memory block, based on the plurality of hit signals HIT<0:9> outputted from the plurality of fuse sets 10_0 to 10_N. The repair processing unit 20 includes a plurality of comparison sections 21_0 to 21_N and a repair determination section 22. The memory block corresponding to the repair address is a memory block where a defect, such as a memory failure, has occurred in a memory read/write operation.
Since all of the comparison sections 21_0 to 21_N perform the same operation, the operation of the first comparison section 21_0 is representatively described. The first comparison section 21_0 outputs a first repair block selection signal HITB<0> by logically combining the plurality of hit signals HIT<0:9> outputted from the first fuse set 10_0. In general, the first comparison section 21_0 includes a logic unit that outputs the first repair block selection signal HITB<0> by performing a NAND operation on the plurality of hit signals HIT<0:9>. Accordingly, when all of the hit signals HIT<0:9> are outputted at a high level, the first repair block selection signal HITB<0> is activated to a low level. This means that the repair address stored in the first fuse set 10_0 is equal to the input address BXAR<2:11>.
The repair determination section 22 outputs repair determination signals HITSUM<0:N> representing whether or not a repair operation is needed, based on the repair block selection signals HITB<0:N> outputted from the plurality of comparison sections 21_0 to 21_N. At that time, assuming that the repair operation is performed on a word line basis, access to normal word lines is prohibited by a normal word line disable signal NWD outputted from the repair determination section 22, and redundancy word lines are driven by a specific repair determination signal HITSUM<i> and replace the normal word lines.
In order to perform the repair operation described above, repair addresses should be programmed into the fuse sets in advance. In general, a programming operation is performed by directly inputting repair addresses from the outside into the fuse sets. However, direct input of the repair addresses into the fuse sets from is the outside reduces the efficiency of the programming operation.